One embodiment of the present invention relates to memory cell and memory architecture design. More specifically, one embodiment of the present invention relates to distributed, configurable modular predecoders used in memory architecture.
Memory architectures typically balance power and device area against speed. High-performance memory architectures thus may place a severe strain on the power and area budgets of associated systems, particularly where such components are embedded within a VLSI system, such as a digital signal processing system for example. Therefore, it is highly desirable to provide a memory architecture that is fast, yet power and area-efficient.
Predecoder blocks are used to perform the first layer of address predecoding, generating the signals used by local decoders (alternatively referred to as “local x and y decoders” or “x and y decoders”) to select specific rows and columns in a memory cell array, and thus select specific memory cells. The parameters of the predecoder block are dependent on how the memory is partitioned. For example, the parameters of the predecoder block are dependent on the number of rows in a subblock, number of subblocks, multiplexing depth, etc. If the predecoder block is implemented in a single contiguous area, the amount of area will vary depending on the exact memory partitioning employed.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with the present invention as set forth in the remainder of the present application with reference to the drawings.